20 beste vacatures voor de functie van engineer (python) – planning & optimization in leuven, vlg (nieuwe medewerkers gezocht)

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Ik wil de nieuwste vacature-alerts ontvangen voor de functie van engineer (python) – planning & optimization in leuven, vlg

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Junior Digital Physical Design / PnR Engineer

ICsense
Leuven

Nu solliciteren

Vacaturegegevens

Kwalificaties

VHDL
Master
Verilog
C
Back-end development
Scripting
SystemVerilog
Python

Volledige vacaturetekst

The job location is Leuven.

The main role of the junior digital physical design / PnR Engineer is to perform and organize the digital and mixed-signal physical design of ASICs developed by ICsense.

Responsibilities

Physical design of digital integrated circuits (place & route) following the internal design rules and quality regulations. Assumes full responsibility on the quality and accurateness of the back-end layouts.

- In close cooperation with analog layouters, digital designers and project leaders
- Organization of deliverables and timings of these deliverables to ensure high-quality and timely delivery of the digital and mixed-signal top-level layout
- Top-level assembly of ASICs containing digital and analog parts, considering DFT
- Top-level physical verification: LVS, DRC, ERC, antenna, IR drop, electro migration…
- Setup and maintain technology setup and tool flow for place & route and physical synthesis

Competences

You have a master’s degree in electrical engineering (preferably chip design)
You are a dynamic and highly motivated engineer
You want to learn all about digital physical design, floor planning and P&R for multiple power-domains (UPF) and multiple clock-domains.
You love automating tools using e.g. a script-based approach (Python, TCL…) to streamline the back-end flow.
You are interested to learn about digital synthesis, logic equivalence checking, Static Timing Analysis and physical verification.
You have strong communication and reporting skills, also in English.
Considered as a plus:
- Experience with front-end RTL design in VHDL and/or Verilog and/or SystemVerilog
- Experience with scripting and programming languages such as Python, TCL and C
- Experience with back-end synthesis and timing analysis (STA)

Our offer

The job location is Leuven
An attractive salary package with a variety of extra benefits
A stimulating and pleasant working environment with regular team activities
A financially healthy company with growth potential
Possibility to continuously learn and grow through in-house and external trainings
Becoming a part of next generation innovative IC developments for international customers in micro-electronics, automotive, medical and industrial companies

Marijke

Think you’d be a great addition to our team? We’d love to hear from you – get in touch and let’s start the conversation.

Back to overview

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engineer (python) – planning & optimization vacatures in leuven, vlg

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Control Systems Engineer

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Senior R&D Engineer (Generative Design & CFD)

Digital Designer — CPU Subsystem (RTL & Verification) (Temporary Assignment)

Analytics Engineer

Senior Digital FE Design Engineer

SCD/3D passive Device Characterization Engineer – Advanced Logic & Superconducting Devices

Mechatronics Engineer

Power Electronics Engineer

Test Automation Engineer

Transport Study Engineer

Ik wil de nieuwste vacature-alerts ontvangen voor de functie van engineer (python) – planning & optimization in leuven, vlg

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